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Title: Dynamically reconfigurable bit parallel pipelined embedded architecture for high speed signal processing
Researcher: Ramadass N
Guide(s): Raja paul perinbam J
Keywords: embedded architecture
information and communication engineering
signal processing
Upload Date: 10-Nov-2014
University: Anna University
Completed Date: 01/03/2008
Abstract: A novel dynamically reconfigurable embedded architecture is newlineproposed in this thesis This architecture is targeted at applications involving newlineinherent data parallelism high regularity and high throughput Realtime newlinedigital signal processing systems are characterized by a large volume of realtime newlinedata input at variable rates and repetitive arithmetic operations on these newlinedata Solutions for such computational problems are mainly driven by the newlinedemanded speed flexibility in architecture and area budget available The newlineproposed architecture uses the concept of resource sharing and dynamic newlinereconfiguration newlineDynamically reconfigurable embedded architecture exploits the newlineconcept of resource sharing thereby achieving more functionality in less area newlinewithout execution time violation newline newline
Pagination: xv, 108p.
Appears in Departments:Faculty of Information and Communication Engineering

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01_title.pdfAttached File39.31 kBAdobe PDFView/Open
02_certificate.pdf5.93 kBAdobe PDFView/Open
03_abstract.pdf9.29 kBAdobe PDFView/Open
04_acknowledgement.pdf6.16 kBAdobe PDFView/Open
05_contents.pdf25.23 kBAdobe PDFView/Open
06_chapter 1.pdf235.44 kBAdobe PDFView/Open
07_chapter 2.pdf288.79 kBAdobe PDFView/Open
08_chapter 3.pdf109.53 kBAdobe PDFView/Open
09_chapter 4.pdf303.57 kBAdobe PDFView/Open
10_chapter 5.pdf1.02 MBAdobe PDFView/Open
11_chapter 6.pdf570.95 kBAdobe PDFView/Open
12_chapter 7.pdf18.55 kBAdobe PDFView/Open
13_references.pdf14.19 kBAdobe PDFView/Open
15_vitae.pdf5.51 kBAdobe PDFView/Open

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