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Title: Parasitic Aware Automatic CMOS Analog Circuit Design Using Evolutionary algorithms
Researcher: Patel Subhash Jagadishchandra
Guide(s): Rajesh A Thakker
Keywords: Engineering and Technology
University: Gujarat Technological University
Completed Date: 20-October-2018
Abstract: The performance of the analog integrated CMOS circuits is very sensitive to design parameters. Its design is a knowledge-intensive trade-off approach and requires lots of expertise. Thus, with increased complexity, the design of high-performance analog circuit becomes a very challenging task. In order to overcome difficulties associated with the analog integrated circuit design, many researchers have used classical and evolutionary algorithms to design analog circuits. However, the designs are limited to schematic-level only. The schematic-level design is an intermediate step of the circuit design process and, generally, based on schematic-level design, the layouts are prepared. Since the layout parasitics are not possible to consider during schematic-level design, the post-layout performance of the circuit differs from the schematic-level performance, especially, for the frequency sensitive specifications. In this work, we propose a novel concept of the parasitic-aware automatic circuit design of analog CMOS circuits that extends the design automation from the schematic-level to layout-level. We have utilized evolutionary algorithms based optimization techniques. The PSO (Particle Swarm Optimization) and ABC (Artificial Bee Colony) algorithms are widely used evolutionary algorithms. Based on these algorithms, we propose two efficient evolutionary algorithms named; MPSO (Modified Particle Swarm Optimization) algorithm and EABC (Enhanced Artificial Bee Colony) algorithm. The MPSO algorithm uses the partial re-initialization scheme to overcome the problem of diversity-loss in PSO algorithm. The EABC algorithm provides faster convergence speed compared to the ABC algorithm. Initially, MPSO, PSO, ABC and EABC algorithms are used to carry out the schematic-level design of the: (1) Two-stage operational amplifier (op-amp), (2) high-gain low voltage bulk-driven OTA, and (3) second generation current conveyor in the 0.13and#956;m and 0.09and#956;m CMOS technologies. The obtained results reveal the effectiveness of the two-stage op-amp
Pagination: 3.8MB
Appears in Departments:Electronics & Telecommunication Enigerring

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01_title.pdfAttached File548.59 kBAdobe PDFView/Open
02_certificate.pdf196.56 kBAdobe PDFView/Open
03_abstract.pdf73.57 kBAdobe PDFView/Open
04_declaration.pdf367.89 kBAdobe PDFView/Open
05_acknowlegement.pdf44.33 kBAdobe PDFView/Open
06_contents.pdf58.5 kBAdobe PDFView/Open
07_list_of_tables.pdf65.59 kBAdobe PDFView/Open
08_list_of_figures.pdf64.67 kBAdobe PDFView/Open
09_list_of_abbreviations.pdf44.03 kBAdobe PDFView/Open
10_chapter1.pdf87.89 kBAdobe PDFView/Open
11_chapter2.pdf228.51 kBAdobe PDFView/Open
12_chapter3.pdf429.27 kBAdobe PDFView/Open
13_chapter4.pdf217.34 kBAdobe PDFView/Open
14_chapter5.pdf1.12 MBAdobe PDFView/Open
15_conclusion.pdf65.81 kBAdobe PDFView/Open
16-bibliography.pdf74.26 kBAdobe PDFView/Open

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