Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/218727
Title: Design and analysis of an efficient architecture of logarithmic multiplier and its applications
Researcher: Nandan,Durgesh
Guide(s): Kanungo,Jitendra and Mahajan, Anurag
Keywords: Algorithm For Logarithmic
Architecture of Logarithmic
Gaussian Smoothing Filter
Improved Operand Decomposition
University: Jaypee University of Engineering and Technology, Guna
Completed Date: 03/10/2018
Abstract: Digital signal processing applications require an efficient errorless and low power arithmetic operation Binary number arithmetic units are compromised on speed complexity Logarithm Number System addresses to these issues and overcome gaps LNS multipliers are advantageous over the Fixed Point multipliers and the Floating Point multipliers in terms of speed and accuracy newlineLNS multiplier has two subcategories newlinea Lookup Tables and Interpolations based multipliers newline b Mitchell s algorithm based multipliers Mitchell s algorithm based logarithm multiplication is further subdivided into four sub-categories As Divided Approximation Correction term based Operand decomposition and MA based iterative algorithm During 2010 to 2013 works on the iterative logarithmic approximation have been proposed It was based on the correction terms with the high level of parallelism with fewer logic resources and higher speed The ASIC implementation of floating point logarithmic number system has also been reported newlineThe computation of arithmetic based on LNS involves three steps Conversion of binary numbers in logarithmic numbers then respective arithmetic operation is performed on logarithmic numbers and then antilogarithmic conversion Many methods regarding logarithmic conversion to binary system and antilogarithmic converter have been presented in recent years Design of Leading-One Detector is important as it is used as a key component for performing shifting and normalization process in the floating point multiplication floating point addition and in binary logarithmic converters Reported LOD designs were either slower or hardware inefficient newlineThe objective of the proposed thesis work is to explore the errorless and low power designs for the implementation of logarithm multiplication and their subcomponents such as logarithm converter and antilogarithm converter An efficient architecture of LOD is also proposed and used in a logarithm multiplier newline
Pagination: xii,116p.
URI: http://hdl.handle.net/10603/218727
Appears in Departments:Department of Electronics and Communication

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10_list of tables.pdfAttached File79.79 kBAdobe PDFView/Open
11_chapter 1.pdf155.98 kBAdobe PDFView/Open
12_chapter 2.pdf195.21 kBAdobe PDFView/Open
13_chapter 3.pdf243.42 kBAdobe PDFView/Open
14_chapter 4.pdf1.61 MBAdobe PDFView/Open
15_chapter 5.pdf521.16 kBAdobe PDFView/Open
16_chapter 6.pdf593.35 kBAdobe PDFView/Open
17_chapter 7.pdf95.49 kBAdobe PDFView/Open
18_bibliography.pdf179.48 kBAdobe PDFView/Open
19_list of publications.pdf111.25 kBAdobe PDFView/Open
1_title.pdf1.9 MBAdobe PDFView/Open
2_table of contents.pdf81.51 kBAdobe PDFView/Open
3_declaration by the scholar.pdf83.87 kBAdobe PDFView/Open
5_acknowledgment.pdf59.11 kBAdobe PDFView/Open
6_synopsis.pdf59.87 kBAdobe PDFView/Open
7_list of acronyms and abbreviations.pdf61.73 kBAdobe PDFView/Open
8_list of symbols.pdf65.69 kBAdobe PDFView/Open
9_list of figures.pdf71.73 kBAdobe PDFView/Open


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