Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/203437
Title: Design and Implementation of efficient Artificial Neural Network architecture for embedded application
Researcher: Prasad S N
Guide(s): Kulkarni S Y
Keywords: Artificial Neural Network
University: Jain University
Completed Date: 11/12/2017
Abstract: Low power gate level data path optimizations are presented for Artificial Neural Network (ANN) architecture to address the low power ANN applications in the field of science and engineering. Efficient 4:2 compressor architecture is proposed for the multiplier architecture of ANN layered structure. Proposed data path architectural optimizations are illustrated in the 2-3-1 three layer artificial neural network (ANN). Verilog HDL was used to model the design in ASIC domain with 65nm technological CMOS library. The proposed concept has resulted with 12.71 % better speed, 15.94 % less area and 26.09 % less leakage power consumption. newline
Pagination: 109p.
URI: http://hdl.handle.net/10603/203437
Appears in Departments:Department of Electronics Engineering

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02. declaration.pdf79.17 kBAdobe PDFView/Open
03. certificate.pdf78.19 kBAdobe PDFView/Open
04. abstract.pdf93.91 kBAdobe PDFView/Open
05. contents.pdf81.76 kBAdobe PDFView/Open
06. chapter - 01.pdf492.78 kBAdobe PDFView/Open
07. chapter - 02.pdf353.41 kBAdobe PDFView/Open
08. chapter - 03.pdf569.1 kBAdobe PDFView/Open
09. chapter - 04.pdf615.31 kBAdobe PDFView/Open
10. chapter - 05.pdf77.32 kBAdobe PDFView/Open
11. chapetr - 06.pdf44.9 kBAdobe PDFView/Open
12. chapetr - 07.pdf44.9 kBAdobe PDFView/Open
15. bibliography.pdf78.77 kBAdobe PDFView/Open


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