Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/188318
Title: Efficient VLSI architectures for DWT and DWPT based on data path study
Researcher: Tiwari,Vikas
Guide(s): Mohanty Basant Kumar
Keywords: Discrete Wavelet Packet Transform
Discrete Wavelet Transform
VLSI Architectures
University: Jaypee University of Engineering and Technology, Guna
Completed Date: 10/12/2017
Abstract: Discrete wavelet transform provides an efficient computing method for sparse representation of wide class of signals The DWT only analyzes the lower frequency sub bands implicitly ignoring any information embedded in the higher frequency sub bands There are few applications where signal information equally distributed in entire signal spectrum such as ultrasound images ECG and EEG images The DWT is expressed in a generalized form know as discrete wavelet packet transform DWPT which analyzes both the low and high sub bands with equal priority at every decomposition level The DWT and DWPT is currently implemented in very large scale integration VLSI system to meet the space time requirement of various real time applications Several design schemes have been suggested for efficient implementation of 2 D DWT and DWPT in a VLSI system Flipping scheme is preferred over the lifting scheme and convolution scheme to design area delay efficient hardware structures for DWT But flipping scheme introduces some design complexities in selected DWT structures A detail datapath study on lifting and flipping DWT is presented in Chapter 3 which is currently missing in the literature Based on the data path study a massively parallel architecture is derived for area-delay efficient implementation of 2D DWT The existing structures proposed for DWPT are mostly two input and two output TITO types The throughput rate of TITO structure changes proportionately with the clock frequency and compromise the throughput rate when it is traded for low power implementation Concurrent design approach can be used to develop parallel architectures for high-throughput implementation Several block based parallel architectures have been proposed using concurrent design approach for implementation 2D DWT but the concurrent design approach not considered for DWPT Chapter 4 addresses this issue and proposes a block-based architecture for computation of multi level 1D DWPT
Pagination: xi,131p.
URI: http://hdl.handle.net/10603/188318
Appears in Departments:Department of Electronics and Communication

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02_certificate.pdf70.98 kBAdobe PDFView/Open
03_preface or abstract.pdf12 kBAdobe PDFView/Open
04_declerartion.pdf69.46 kBAdobe PDFView/Open
05_acknowledgement.pdf9.91 kBAdobe PDFView/Open
06_contents.pdf16.45 kBAdobe PDFView/Open
07_list of table.pdf13.85 kBAdobe PDFView/Open
08_list of figure.pdf17.57 kBAdobe PDFView/Open
09_ abreviations.pdf59.72 kBAdobe PDFView/Open
10_chapter 1.pdf218.74 kBAdobe PDFView/Open
11_chapter 2.pdf145.06 kBAdobe PDFView/Open
12_chapter 3.pdf571.62 kBAdobe PDFView/Open
13_chapter 4.pdf761.56 kBAdobe PDFView/Open
14_chapter 5.pdf318.26 kBAdobe PDFView/Open
15_chapter 6.pdf287.12 kBAdobe PDFView/Open
16_chapter 7.pdf106.72 kBAdobe PDFView/Open
17_summary.pdf106.13 kBAdobe PDFView/Open
18_biblography.pdf152.23 kBAdobe PDFView/Open
19_list of publication.pdf13.12 kBAdobe PDFView/Open


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