Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/187118
Title: Parallel VLSI architecture for lifting 2D DWT using radix 8 booth multiplier
Researcher: Choubey Abhishek
Guide(s): Mohanty Basant Kumar
Keywords: Discrete Wavelet Transform
Multiplexer Design
VLSI Architecture
University: Jaypee University of Engineering and Technology, Guna
Completed Date: 27/12/2017
Abstract: The discrete wavelet transform is a multi-resolution analysis tool widely used in signal analysis such as image compression speech analysis and pattern recognition Several design schemes have been proposed in the last two decades for efficient implementation of 2D DWT in VLSI system Researchers have adopted different algorithm formulation mapping scheme and architectural design methods such as PA and RPA based folded based parallel designs and multiplier less designs to reduce the computational time arithmetic or memory complexities of 2D DWT Among these designs parallel design offers a better utilization of memory resource which is a major component in multilevel 2D DWT structure Memory complexity is considered to be the design issue and overlapping data accessing scheme is considered to reduce on chip memory aggressively at the cost of some overhead complexity However the parallel design uses several data selectors multiplexors and de-multiplexors apart from multiplier adder and memory elements These data selectors are used for time multiplexing data sequences to improve the resource utilization of the hardware design while performing down sample filter computation The data selector complexity depends on the block size which is usually very large and mapping algorithm The data selector complexity affects the area-delay efficiency of the parallel design substantially However the data selector complexity somehow is overlooked in the existing parallel designs Using appropriate algorithm formulation and architecture design the data selector complexity can be avoided completely to improve the hardware efficiency of the parallel designs without considering aggressive memory optimization with overhead complexity Also it is observed that that the parallel design for large block size involves hundreds of multipliers which contribute almost comparable amount area as the onchip memory unit Use of an optimized multiplier design could improve the are adelay efficiency of the parallel design substantially
Pagination: x,130p.
URI: http://hdl.handle.net/10603/187118
Appears in Departments:Department of Electronics and Communication

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02_certificate.pdf55 kBAdobe PDFView/Open
03_abstract.pdf53.44 kBAdobe PDFView/Open
04_declaration.pdf55 kBAdobe PDFView/Open
05_acknowledgement.pdf35.06 kBAdobe PDFView/Open
06_contents.pdf126.41 kBAdobe PDFView/Open
07_list_of_figures..pdf80.83 kBAdobe PDFView/Open
08_list_of_table.pdf106.68 kBAdobe PDFView/Open
09_abbreviations.pdf30.34 kBAdobe PDFView/Open
10_chapter1.pdf295.4 kBAdobe PDFView/Open
11_chapter2.pdf196.89 kBAdobe PDFView/Open
12_chapter3.pdf579.96 kBAdobe PDFView/Open
13_chapter4.pdf443 kBAdobe PDFView/Open
14_chapter5.pdf619.79 kBAdobe PDFView/Open
15_chapter6.pdf859.86 kBAdobe PDFView/Open
16_chapter7.pdf134.99 kBAdobe PDFView/Open
17_conclusion.pdf64.37 kBAdobe PDFView/Open
18_bibliography.pdf275.46 kBAdobe PDFView/Open
19_list of publication.pdf107.94 kBAdobe PDFView/Open


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