Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/183750
Title: Power and performance aware on chip interconnection architectures for many core systems
Researcher: Mondal, Hemanta Kumar
Guide(s): Deb, Sujay
Keywords: Chip
Interconnection architectures
Network
University: Indraprastha Institute of Information Technology, Delhi (IIIT-Delhi)
Completed Date: 2017
Abstract: File attached
Pagination: 135 p.
URI: http://hdl.handle.net/10603/183750
Appears in Departments:Electronics and Communication Engineering

Files in This Item:
File Description SizeFormat 
01_title.pdfAttached File38.52 kBAdobe PDFView/Open
02_certificate.pdf111.72 kBAdobe PDFView/Open
03_dedication.pdf74.8 kBAdobe PDFView/Open
04_acknowlegement.pdf113.85 kBAdobe PDFView/Open
05_abstract.pdf40.23 kBAdobe PDFView/Open
06_publications.pdf124 kBAdobe PDFView/Open
07_content.pdf170.11 kBAdobe PDFView/Open
08_list of figures and tables.pdf298.28 kBAdobe PDFView/Open
09_chapter 1.pdf580.42 kBAdobe PDFView/Open
10_chapter 2.pdf1 MBAdobe PDFView/Open
11_chapter 3.pdf1.3 MBAdobe PDFView/Open
12_chapter 4.pdf1.01 MBAdobe PDFView/Open
13_chapter 5.pdf617.31 kBAdobe PDFView/Open
14_chapter 6.pdf53.54 kBAdobe PDFView/Open
15_bibliography.pdf265.13 kBAdobe PDFView/Open


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