Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/18186
Title: Memory efficient concurrent vlsi architectures for two dimensional discrete wavelet transform
Researcher: Mahajan, Anurag
Guide(s): Mohanty,Basant Kumar
Keywords: Hardware complexity analysis
Low complexity design
VLSI architectures
Wavelet transform
Upload Date: 7-May-2014
University: Jaypee University of Engineering and Technology, Guna
Completed Date: 29/10/2013
Abstract: Discrete wavelet transform (DWT) is a mathematical technique that provides a new method for signal processing. Due to various useful features like adaptive time-frequency window, lower aliasing distortion and efficient computational complexity, it is widely used in many signal and image processing applications. Two-dimensional (2-D) DWT is highly computation intensive and many of its application need real-time processing to deliver better performance. Therefore, 2-D DWT is currently implemented in very large scale integration (VLSI) system to meet the space-time requirement of various real-time applications. Various algorithms and architectures have been proposed in the last decade for efficient implementation of multilevel 2-D DWT. The hardware complexity of 2-D DWT structure is broadly divided into two parts (i) arithmetic and (ii) memory. The complexity of 2-D DWT structure is dominated by the complexity of memory component. However, most of the existing design strategies are focused on arithmetic complexity, cycle period and throughput. There is no specific memory-centric design method is proposed for multilevel 2-D DWT. The objective of the proposed thesis work is to explore memory-centric design approaches. Four separate design approaches and concurrent architectures are proposed in this thesis for area-delay-power efficient implementation of multilevel 2-D DWT. newlineIn Chapter 3, a block processing scheme is proposed to improve the on-chip memory and frame buffer utilization efficiency of line-based folded 2-D DWT structure. A line-based parallel and pipeline structure is derived using the proposed block processing scheme. On-chip and frame buffer size of the proposed line-based structure is independent of input block size and it is easily configured for any block sizes. In Chapter 4, a new data access scheme is proposed to reduce the size of transposition memory and introduce embedded down-sampling in the DWT computation. Using the proposed data access scheme, an area-delay efficient structure.
Pagination: 
URI: http://hdl.handle.net/10603/18186
Appears in Departments:Department of Electronics and Communication

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01_title.pdfAttached File38.28 kBAdobe PDFView/Open
02_certificate.pdf40.84 kBAdobe PDFView/Open
03_abstract.pdf70.21 kBAdobe PDFView/Open
04_declaration.pdf26.03 kBAdobe PDFView/Open
05_acknowledgement.pdf30.14 kBAdobe PDFView/Open
06_contents.pdf115.23 kBAdobe PDFView/Open
07_list of tables.pdf79.77 kBAdobe PDFView/Open
08_list of figures.pdf123.72 kBAdobe PDFView/Open
09_list of abbreviations.pdf68.99 kBAdobe PDFView/Open
10_list of symbols.pdf112.61 kBAdobe PDFView/Open
11_chapter 1.pdf734 kBAdobe PDFView/Open
12_chapter 2.pdf703.3 kBAdobe PDFView/Open
13_chapter3.pdf1.04 MBAdobe PDFView/Open
14_chapte 4.pdf1.01 MBAdobe PDFView/Open
15_chapter 5.pdf1.21 MBAdobe PDFView/Open
16_chapter 6.pdf964.32 kBAdobe PDFView/Open
17_chapter 7.pdf119.54 kBAdobe PDFView/Open
18_ bibliography.pdf412.3 kBAdobe PDFView/Open
19_conclusion.pdf119.48 kBAdobe PDFView/Open
20_summary.pdf632 kBAdobe PDFView/Open
21_list of publications.pdf30.14 kBAdobe PDFView/Open


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