Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/149626
Title: FPGA Based Novel Implementation of FIR Filter using Improved Reconfigurable Distributed Arithmetic Algorithm for Efficient Communication Application
Researcher: Bhagyalakshmi N.
Guide(s): Rekha K.R.
Keywords: Finite Impulse
FPGA
University: Jain University
Completed Date: 12/11/2016
Abstract: Research work focuses on the development of the Improved Reconfigurable Distributed Arithmetic architecture based Finite Impulse Response filter and its implementation for updown frequency converters in communication systems Traditional DSP based FIR filter implementation constituted MAC unit Multiplier implementation on FPGA essentially requires large chip area with increased power consumption reduction in throughput with increase in number of filter tap filter length resulting in reduction of sampling rate newline
Pagination: 140p.
URI: http://hdl.handle.net/10603/149626
Appears in Departments:Department of Electronics Engineering

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01.title page.pdfAttached File171.79 kBAdobe PDFView/Open
02.declaration.pdf352.83 kBAdobe PDFView/Open
03.certificate.pdf250.1 kBAdobe PDFView/Open
04.acknowledgement.pdf179.43 kBAdobe PDFView/Open
05.abstract.pdf95 kBAdobe PDFView/Open
06.contents.pdf100.86 kBAdobe PDFView/Open
07.list of figures and tables.pdf203.27 kBAdobe PDFView/Open
08.chapter 1.pdf329.32 kBAdobe PDFView/Open
09.chapter 2.pdf239.62 kBAdobe PDFView/Open
10.chapter 3.pdf885.45 kBAdobe PDFView/Open
11.chapter 4.pdf705.43 kBAdobe PDFView/Open
12.chapter 5.pdf463.76 kBAdobe PDFView/Open
13.chapter 6.pdf2.51 MBAdobe PDFView/Open
14.chapter 7 & 8.pdf1.55 MBAdobe PDFView/Open
15.bibliography.pdf368.08 kBAdobe PDFView/Open


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